Method and apparatus for verifying the programming of multi-leve

Details Method and apparatus for verifying the programming of multi-leve Method and apparatus for verifying the programming of multi-leve

1994-06-02

1996-06-04

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 36518907, 365201, G11C 2900

Patent

active

055239722

ABSTRACT:
A programming verify circuit for controlling the memory cells to which programming voltages are applied, the circuit including a comparator for testing the state of each cell being programmed with the state to which the cell is being programmed, and a program load circuit which responds to the result of the test by the comparator to hold a condition for each memory cell being programmed to indicate whether the memory cell should be further programmed, each program load circuit including circuitry for precluding the holding of a condition indicating further programming is necessary once the associated memory cell has been initially verified as programmed by the comparator.

REFERENCES:
patent: 5287317 (1994-02-01), Kobayashi et al.
patent: 5293610 (1994-03-01), Schwarz

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