Patent
1991-08-15
1992-08-25
Carroll, J.
357 235, 357 2314, 357 41, H01L 2968, H01L 2906, H01L 2702
Patent
active
051423456
ABSTRACT:
Disclosed is a structure of a semiconductor device in which an internal circuit including a memory device and a transistor having an LDD structure, and an input protection device for protecting the internal circuit are formed on one semiconductor substrate, and a method of manufacturing such a semiconductor device. The input protection device and the memory device are formed at the same time. The input protection device as well as the memory device includes source/drain regions formed of high concentration impurity regions and formed in the surface of the semiconductor substrate, and a gate electrode formed of a plurality of conductor films and formed on the surface of the semiconductor substrate between the source/drain regions. When an abnormal voltage is applied to an interconnection for supplying an electrical signal to the internal circuit, a charge flows from the interconnection through one source/drain region of the input protection device into the semiconductor substrate, so that the internal circuit is protected against an excessive charge.
REFERENCES:
patent: 4663645 (1987-05-01), Komori et al.
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4835597 (1989-05-01), Okuyama et al.
Carroll J.
Mitsubishi Denki & Kabushiki Kaisha
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