Semiconductor test interface

Details Semiconductor test interface Semiconductor test interface

2007-10-30

2007-10-30

Nguyen, Ha Tran (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

11275768

ABSTRACT:
The present invention relates to a semiconductor test interface for interfacing a DUT (Device Under Test) to a pin card using a cable comprising a DUT board including one or more first connectors for electrically connecting one or more test sockets for mounting the DUT to the one or more cables, and a circuit wiring for electrically connecting the one or more test sockets to the one or more first connectors; and the one more cable including a second connector for an electrical connection to the one or more first connectors, and a third connector for an electrical connection to the pin card, wherein the one or more first connectors correspond to the one or more cables by 1:1.In accordance with the present invention, the manufacturing cost is reduced by simplifying the manufacturing process and the semiconductor test interface may easily correspond to the test of the different DUTs.

REFERENCES:
patent: 6348789 (2002-02-01), Terao
patent: 6552528 (2003-04-01), Frame
patent: 6822436 (2004-11-01), Frame
patent: 2002/0130653 (2002-09-01), Frame
patent: 2003/0090259 (2003-05-01), Frame
patent: 2005/0040811 (2005-02-01), Frame

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