Semiconductor memory device

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S154000, C365S156000, C365S230030, C365S230050

Reexamination Certificate

active

10879753

ABSTRACT:
A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read global bit line through the read section. The write section is shared by at least two memory cells in the same memory cell group. Thus, writing of data in a memory cell is desirably achieved although the memory cell has a common 6-transistor structure.

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patent: 2002-100187 (2002-04-01), None
Zhang, Kevin., et al. “the Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18um Technologies.” Symposium on VLSI Circuits Digest of Technical Papers, 2000, pp. 2.
Silberman, Joel., et al. “A 1.6 ns Access, 1 GHz Two-Way Set-Predicted and Sum Indexed 64-kByter Data Cache.” Symposium on VLSI Circuits Digest of Technical Papers, 2000, pp. 2.
Japanese Office Action for Corresponding Application No. JP 2003-190052 Mailed Feb. 20, 2007.

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