Scan line conversion circuit for simultaneously carrying out...

Details Scan line conversion circuit for simultaneously carrying out... Scan line conversion circuit for simultaneously carrying out...

Filed on

2007-06-26

Date issued

2007-06-26

Examiner

Kostak, Victor R. (Department: 2622)

Patent Class

Television

SubClass

Format conversion

SubSubClass

Line doublers type

Other Related Categories

C348S452000, C348S458000

Type

Reexamination Certificate

Status

active

Patent number

11281487

Description

ABSTRACT:
A scan line conversion circuit is provided for simultaneously carrying out three-dimensional motion adaptive sequential scan conversion and scan line conversion. The scan line conversion circuit comprises an FIFO memory into which the video signal is input; a sequential scan conversion circuit section for converting an interlace signal sent from the FIFO memory to a non-interlace signal; an address generator into which a vertical enlargement ratio and a synchronous signal are input to generate an address as a spatial position after scan line conversion; a memory control unit for generating a memory control signal based on the address sent from the address generator; a coefficient generator for generating a coefficient for performing scan line conversion; a plurality of first multipliers for multiplying sequentially scan converted signals, sent from the sequential scan conversion circuit section, by respective coefficients; and an adder for adding signals output from the multipliers together.

REFERENCES:
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patent: 6356310 (2002-03-01), Horishi et al.
patent: 6380978 (2002-04-01), Adams et al.
patent: 2000-253365 (2000-09-01), None

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