Semiconductor device including fine dummy patterns

Details Semiconductor device including fine dummy patterns Semiconductor device including fine dummy patterns

2007-06-19

2007-06-19

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S758000, C257S773000

Reexamination Certificate

active

11082853

ABSTRACT:
A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

REFERENCES:
patent: 5519250 (1996-05-01), Numata
patent: 5861674 (1999-01-01), Ishikawa
patent: 6396146 (2002-05-01), Nakayama
patent: 08-181208 (1996-07-01), None

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