Gate-enhanced junction varactor

Details Gate-enhanced junction varactor Gate-enhanced junction varactor

2007-06-26

2007-06-26

Baumeister, B. William (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Voltage variable capacitance device

C257SE29344

Reexamination Certificate

active

09903059

ABSTRACT:
A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

REFERENCES:
patent: 4003009 (1977-01-01), Watanabe
patent: 4529994 (1985-07-01), Sakai
patent: 5399893 (1995-03-01), Weitzel et al.
patent: 5497028 (1996-03-01), Ikeda et al.
patent: 5504376 (1996-04-01), Sugahara et al.
patent: 5659185 (1997-08-01), Iwamuro
patent: 5977591 (1999-11-01), Fratin et al.
patent: 6100770 (2000-08-01), Litwin et al.
patent: 6165902 (2000-12-01), Pramanick et al.
patent: 6166404 (2000-12-01), Imoto et al.
patent: 6455902 (2002-09-01), Voldman
patent: 2002/0036311 (2002-03-01), Hattori
patent: 2003/0178689 (2003-09-01), Maszara et al.
patent: 04199682 (1992-09-01), None
patent: 406061446 (1994-03-01), None
patent: 407226643 (1995-08-01), None
Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits 1998, Oxford University Press, Inc., 4thedition, p. 382.
Andreani, et al., “A 1.8-GHZ CMOS VCO Tuned by an Accumulation-Mode MOS Varactor,” IEEE Intl. Symposium on Circuits and Systems, May 28-31, 2000, pp. I-315-I-318.
Grove,Physics and Technology of Semiconductor Devices(John Wiley & Sons), 1967, pp. 263-305.
Grove, et al., “Effect of Surface Fields on the Brakdown Voltage of Planar Siliconp-nJunction,”IEEE Trans. Electron Devices, vol. ED-14 ,1967, pp. 157-162.
Grove, et al., “Surface Effects onp-nJunctions: Characteristics of Surface Space-Charge Regions Under Non-Equilibrium Conditions,”Solid-State Electronics, vol. 9, 1966, pp. 783-806.
Kral, et al., “RF-CMOS Oscillators with Switched Tuning,”Procs. IEEE Custon Integrated Circuits Conference, 1998, pp. 555-558.
Lee,The Design of CMOS Radio-Frequency Integrated Circuits(Cambridge Univ. Press), 1998, pp. 37-41 and 504-514.
McMahon, et al., “Voltage-Sensitive Semiconductor Capacitors,”1958 IRE Wescon Conf. Rec., Part 3, Aug. 19-22, 1958, pp. 72-82.
Moll, “Variable Capacitance With Large Capacity Change”,IRE Wescon Conf. Rec., vol. 3, 1959, pp. 32-36.
Ng,Complete Guide to Semiconductor Deices(McGraw Hill), 1995, pp. 11-22.
Razavi,Design of Analog CMOS Integrated Circuits(McGraw Hill), 2001, pp. 495-525.
Rusu et al., “Deep-Depletion Breakdown Voltage of Silicon-Dioxide/Silicon MOS Capacitors”,IEEE Trans. Elec. Devs., Mar. 1979, pp. 201-205.
Rusu et al., “Reversible Breakdown Voltage Collapse in Silicon Gate-Controlled Diodes”Solid-State Electronics, vol. 23, 1980, pp. 473-480.
Svelto, et al., “A Three Terminal Varactor for RF IC's in Standard CMOS Technology,”IEEE Transactions on Electron Devices, vol. 47, 2000, pp. 893-895.
Warner, Jr., et al.,Transistors—Fundamentals for the Integrated-Circuit Engineer(John Wiley & Sons), 1983, pp. 320-321.
Wong et al., “A Wide Tuning Range Gated Varactor”,IEEE J. Solid State Circs., May 2000, pp. 773-779.

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