Use of recovery transistors during write operations to...

Details Use of recovery transistors during write operations to... Use of recovery transistors during write operations to...

2007-11-13

2007-11-13

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185180, C365S185250, C365S185280

Reexamination Certificate

active

11303368

ABSTRACT:
A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array has a plurality of memory cells, each of which is coupled to a unique array bitline. A unique recovery transistor is coupled to each array bitline. The recovery transistors on odd bitlines are coupled to a first and second voltage, while the recovery transistors on even bitlines are coupled to a first and third voltage. During a write operation, each recovery transistor coupled to an unselected bitline is active during a write operation and a recovery operation, while each recovery transistor coupled to a selected bitline is active during a recovery operation. The first voltage is sufficient to prevent parasitic coupling between the selected bitlines and the unselected bitlines during the write operation.

REFERENCES:
patent: 5598369 (1997-01-01), Chen et al.
patent: 5642310 (1997-06-01), Song
patent: 5831896 (1998-11-01), Lattimore et al.
patent: 6704239 (2004-03-01), Cho et al.
patent: 2006/0083064 (2006-04-01), Edahiro et al.

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