Semiconductor device and cell

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means

Reexamination Certificate

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Details

C257S202000, C257S210000, C257SE23153

Reexamination Certificate

active

11024464

ABSTRACT:
A cell100includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals151and output terminals152for connecting the cell to another cell are formed includes a power supply line passing region153through which a power supply line for supplying a power supply voltage and a ground voltage from an external power supply to the transistors in the cell can be provided.

REFERENCES:
patent: 5619048 (1997-04-01), Yokota et al.
patent: 6296088 (2001-10-01), Carlson
patent: 6677649 (2004-01-01), Osada et al.
patent: 6794674 (2004-09-01), Kusumoto
patent: 6-088854 (1994-03-01), None
patent: 2002-261245 (2002-09-01), None

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