Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Patent
1994-06-24
1996-06-04
Callahan, Timothy P.
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
327434, 327513, 327309, 327328, H03K 17687, H03K 342, H03K 508
Patent
active
055237142
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a monolithically integrated MOS output-stage component, particularly a DMOS output stage, having an output-stage element with a GATE connection, A SOURCE connection and a DRAIN connection, and having an overload-protection device.
Overload-protection devices are known in various discrete circuit variants. In this connection, specific adaptation to the specific output-stage component requires a significant expense and the physical limits of the semiconductor can only be utilized to a limited extent.
SUMMARY OF THE INVENTION
A MOS output-stage component according to the present invention has the advantage of being inexpensive to produce as a result of a monolithically integrated solution with improved protective function and greater utilization of the physical limits of the semiconductor. As a result of the level adaptation stage, there is a sufficiently high supply voltage available for the dependable operation of the overload or power limitation in order to limit the loss power to a value of zero. The input voltage (GATE-SOURCE voltage of the output-stage component) or the sense current from a sense cell of the output-stage component can be utilized as measurement value for the output or DRAIN current Id. The level adaptation may be effected by balancing, in the manner that the control characteristic Id=f (Ugs) has a negative temperature coefficient and limits, while stabilizing, the output current upon an increase in the temperature of the chip. This can be effected, for instance, by suitable selection of the temperature coefficient of a source of reference voltage or by suitable combination of the resistor temperature coefficients of the resistors involved.
The level adaptation stage is advantageously developed as a current level, the first branch of which connects the GATE connection of the output-stage component with the SOURCE connection and the second branch of which is acted on by a reference current. For this purpose, a source of reference current is connected to this second branch, it being fed from the outer GATE connection. In this way, the integrated GATE series resistor is controlled with a defined flow and the level adaptation formed thereby shifts the transmission characteristic of the output stage by a defined voltage offset value and increases the external threshold value of the output stage. In other words, no output current below this value flows in the output stage. At the same time, the fixed association Ugs=f (Id) is produced, so that the input voltage Ugs can be used as measurement value for the output current Id flowing.
The loss power which is to be monitored amounts to P=Uds.multidot.Id. It could be exactly determined with an analog multiplier, but this is very expensive and scarcely possible in integrated form. For the limit conditions existing here in combination with the level adaption stage, an adder stage which additively connects the DRAIN-SOURCE voltage to the GATE-SOURCE voltage is sufficient to produce a good approximate solution for the multiplication and formation of the power or load to be limited in a manner which is very simple from a circuit standpoint. For this purpose, the adder stage includes two resistors which are connected on one side to each other and over which the two voltages are brought together at a summation point.
As an alternative to the voltage Ugs, there can also be used as measure of the DRAIN current that voltage which produces a sense current Is=Id/k which flows through sense cells in the SOURCE region of the output-stage element by flow into the summation point of the control circuit.
In order to reduce the power when necessary, the limiting stage has means for reducing the resistance of a MOS transistor connected between the outer GATE connection and the SOURCE connection upon an increase in the sum value of the adder stage. In this way, the control potential is reduced until the sum voltage which is proportional to the power agrees with a reference value.
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REFERENCES:
patent: 4893158 (1990-01-01), Mihara et al.
patent: 4896199 (1990-01-01), Tsuzuki et al.
patent: 4926283 (1990-05-01), Qualich
patent: 5272399 (1993-12-01), Tihanyi et al.
patent: 5352932 (1994-10-01), Tihanyi
Topp Rainer
Uebele Manfred
Callahan Timothy P.
Phan Trong
Robert & Bosch GmbH
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