Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2007-12-25

2007-12-25

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

11015813

ABSTRACT:
Disclosed is an ESD protection circuit for use in a semiconductor memory device with enhanced ESD efficiency. The ESD protection circuit includes: an input pad for receiving a data; a data input buffer for transmitting the data inputted from the input pad to an internal circuit; a first discharging means for a HBM/MM ESD connected to the input pad; and a second discharging means provided with at least one diode for a CDM ESD, disposed between the first discharging means and the data input buffer.

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