Integrated circuit with an electrostatic discharge...

Details Integrated circuit with an electrostatic discharge... Integrated circuit with an electrostatic discharge...

2007-06-19

2007-06-19

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C361S091100, C257S355000, C257S356000

Reexamination Certificate

active

11279572

ABSTRACT:
MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.

REFERENCES:
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patent: 5521789 (1996-05-01), Ohannes et al.
patent: 5528188 (1996-06-01), Au et al.
patent: 6072219 (2000-06-01), Ker et al.
patent: 6465768 (2002-10-01), Ker et al.
patent: 6469353 (2002-10-01), Amerasekera et al.
Charvaka Duvvury et al, “Substrate Pump NMOS for ESD Protection Applications.”, EOS/ESD Symposium, pp. 1A.2.1-1A.2.11, Silicon Technology Development, Texas Instruments, Dallas, Texas.
Ming-Dou Ker, Tung-Yang Chen. “Substrate-Triggered ESD Protection Circuit Without Extra Process Modification.”, IEEE Journal of Solid-State Circuits, Feb. 2003, pp. 295-302, vol. 38, No. 2.

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