Estimation circuit for time-interleaved ADC and method thereof

Details Estimation circuit for time-interleaved ADC and method thereof Estimation circuit for time-interleaved ADC and method thereof

2007-08-07

2007-08-07

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000

Reexamination Certificate

active

11279556

ABSTRACT:
The present invention provides an apparatus and a method for estimating at least one of timing, gain, and offset errors of a time-interleaved ADC. The apparatus has a first ADC, a second ADC, a converter, an estimator, and a compensator. The converter has a Fourier Transform converter and a calculator.

REFERENCES:
patent: 4763105 (1988-08-01), Jenq
patent: 5239299 (1993-08-01), Apple et al.
patent: 5294926 (1994-03-01), Corcoran
patent: 6384756 (2002-05-01), Tajiri et al.
patent: 6452518 (2002-09-01), Kawabata
patent: 6700515 (2004-03-01), Asami
patent: 6809668 (2004-10-01), Asami
patent: 2000059219 (2000-02-01), None
patent: 00456108 (2001-09-01), None
Antonio Petraglia and Sanjit K. Mitra., “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer.”, IEEE Trans on Instrum. and Meas., Oct. 1991, pp. 831-835, vol. 40, No. 5, 1991 IEEE.
Brad Booth et al, “IEEE 802 10GBASE-T Tutorial,”, Nov. 10, 2003, pp. 1-56.
D. Fu, et al., “A digital background calibration technique for time-interleaved analog-to-digital converters.”, IEEE J. of Solid-State Circuits, Dec. 1998, pp. 1904-1911, vol. 33, No. 12, 1998 IEEE.
Huawen Jin, Edward K. F. Lee, “A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC's.”, IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Jul. 2000, pp. 603-613, vol. 47, No. 7, 2000 IEEE.
J. Elbornsson et al, “Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system.” Trans. on Circuits and Systems-I: Regular Papers, Jan. 2004, pp. 151-158, vol. 51, No. 1, 2004 IEEE.
N. Kurosawa et al, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems.” IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications., Mar. 2001, pp. 261-271, vol. 48, No. 3, 2001 IEEE.
Yih-Chyun Jenq., “Digital Spectra of nonuniformly sampled signals: fundamentals and high-speed waveform digitizers.”, IEEE Trans. on Instrum. and Meas., Jun. 1988, pp. 245-251, vol. 37, No. 2, 1988 IEEE.
Yih-Chyun Jenq., “Digital spectra of nonuniformly sampled signals: A robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving.”. IEEE Trans. on Instrum. and Meas., Feb. 1990, pp. 71-75, vol. 39, No. 1 1990 IEEE.

Affiliated with

Also associated with

Rating

Estimation circuit for time-interleaved ADC and method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Estimation circuit for time-interleaved ADC and method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Estimation circuit for time-interleaved ADC and method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3858933