Digital filters with reduced multiplier circuitry

Details Digital filters with reduced multiplier circuitry Digital filters with reduced multiplier circuitry

1980-05-09

1982-03-30

Malzahn, David H.

Boots, shoes, and leggings

G06F 1531

Patent

active

043228100

ABSTRACT:
A digital filter comprises a circuit means for applying a plurality of binary coded weights to a binary coded input data. The circuit means is constructed such that any of integer amounting to the number of bits of the binary coded weight data or to the number of partial bits divided from the weight data is multiplied by the binary coded input data and a result of the multiplication is stored in a memory device in an address thereof corresponding to the integer, that the memory device is accessed by an address of the weight data or the partial bit, and that the digit of the data read out of the memory device is shifted and accumulated to produce a product of the input data and weight data. A product regarding a preceding input data and that regarding a succeeding input data are added together to produce a filter output.

REFERENCES:
patent: 3777130 (1973-12-01), Croisier et al.
patent: 3988606 (1976-10-01), Eggermont
patent: 4125900 (1978-11-01), Betts
patent: 4255794 (1981-03-01), Nakayama
Tubiana, "Digital Filter", IBM Tech. Disclosure Bulletin, vol. 17, No. 9, Feb. 1975, pp. 2656-2658.

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