Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2007-12-04
2007-12-04
Jain, Raj K (Department: 2616)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S229000, C370S230000, C370S230100, C370S231000, C370S235000, C370S465000, C370S474000, C370S476000, C370S471000, C370S470000, C709S232000, C709S234000, C709S236000
Reexamination Certificate
active
10813731
ABSTRACT:
Disclosed is a system and method for assembling a data packet. The system can be implemented as four memory elements associated with one or more processors. The first memory element stores a sequence number and a sub-channel identifier for an incoming data packet. The second memory element stores a revised packet fragment. The third memory element stores an unrevised packet fragment. The fourth memory element stores a starting address. In the system, the starting address may be the starting address of the revised packet fragment or the unrevised packet fragment wherein the first memory element identifies portions of the fourth memory element associated with the sequence number. The one or more processors are configured to create a modified data packet by combining the unrevised packet fragments and the revised packet fragment, wherein the modified data packet is associated with the sequence number and sub-channel identifier.
REFERENCES:
patent: 6034957 (2000-03-01), Haddock et al.
patent: 6295299 (2001-09-01), Haddock et al.
patent: 6381242 (2002-04-01), Maher, III et al.
patent: 6781992 (2004-08-01), Rana et al.
patent: 6795435 (2004-09-01), Jouppi et al.
patent: 6914905 (2005-07-01), Yip
patent: 6917617 (2005-07-01), Jin et al.
patent: 6957258 (2005-10-01), Maher, III et al.
patent: 2002/0095512 (2002-07-01), Rana et al.
patent: 2003/0193949 (2003-10-01), Kojima et al.
patent: 2004/0003110 (2004-01-01), Ozguner
patent: 2004/0246981 (2004-12-01), Zhiqun
patent: 2005/0074009 (2005-04-01), Kanetake
patent: WO 03/081857 (2003-10-01), None
Van Ess, D.,A Circular FIFO, PSoC Style, Cypress Microsystems, Application Note AN2036, Rev. B, pp. 1-5, Jun. 21, 2002.
Network Working Group,RFC 1071—Computing the Internet Checksum, Sep. 1988,available at:http://www.faqs.org/rfcs/rfc1071.html.
Network Working Group,RFC 1141—Incremental Updating of the Internet Checksum, Jan. 1990,available at:http://www.faqs.org/rfcs/rfc1141.html.
Network Working Group,RFC 1624—Computation of the Internet Checksum via Incremental Update, May 1994,available at:http://www.faqs.org/rfcs/rfc1624.html.
Netlogic Microsystems, Product Brief NSE5000GLQ, Copyright 2004,available at: http://www.netlogicmicro.com/datasheets
se5000glq.html.
Zhang, Z.,Recovery of Memory and Process in DSM Systems: HA Issue #1, Hewlett-Packard Co. HPL-2001-76, Mar. 30, 2001.
Swenson Erik R.
Young Christopher J.
Extreme Networks, Inc.
Howrey LLP
Jain Raj K
LandOfFree
System and method for assembling a data packet does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for assembling a data packet, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for assembling a data packet will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3857825