Simulator system for logic design validation

Details Simulator system for logic design validation Simulator system for logic design validation

1982-10-22

1985-07-02

Krass, Errol A.

Boots, shoes, and leggings

324 73R, 364481, 371 23, G06G 748, G06F 1516

Patent

active

045272492

ABSTRACT:
A hardware network or system is disclosed for testing LSI and VLSI logic device design and system design by simulation utilizing individual gate functions. The simulator system uses switching logic, random access memory, and a state table device to simulate particular test routines to test device design with functions which may appear in random or semi-random sequence.

REFERENCES:
patent: 4293919 (1981-10-01), Dasgupta et al.
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4365334 (1982-12-01), Smith et al.
patent: 4428060 (1984-01-01), Blum
patent: 4450560 (1984-05-01), Conner
Angus R. McKay, "Comment on `Computer-aided Design: Simulation of Digital Design Logic,`" IEEE Transactions on Computers, Sep. 1969, p. 862.
R. Barto et al., "A Computer Architecture for Digital Logic Simulation," Electronic Engineering, Sep. 1980, p. 35.

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