Unified shared pipeline allowing deactivation of RISC/DSP...

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...

Reexamination Certificate

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C713S324000

Reexamination Certificate

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10651234

ABSTRACT:
An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.

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