Method for qualifying biased integrated circuits on a wafer leve

Details Method for qualifying biased integrated circuits on a wafer leve Method for qualifying biased integrated circuits on a wafer leve

1979-12-21

1981-09-15

Weisstuch, Aaron

Metal working

Method of mechanical manufacture

Assembling or joining

29583, 29591, 250492A, 324158T, H01L 2166, H01L 21423

Patent

active

042889111

ABSTRACT:
Integrated circuits in dice on a wafer are qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during exposure to a qualifying environment, testing the fusible elements, removing the conductors and testing the circuits. Where the environment is gamma radiation, the fusible elements are tested before annealing of radiation damage and the circuits are tested before and after annealing.

REFERENCES:
patent: 3461547 (1969-08-01), Di Curcio
patent: 3553830 (1971-01-01), Jenny et al.
patent: 3723873 (1973-03-01), Witteles
patent: 3769693 (1973-11-01), Cates et al.
patent: 3849872 (1974-11-01), Hubacher
patent: 4032949 (1977-06-01), Bierig
patent: 4172228 (1979-10-01), Gauthier et al.
patent: 4220918 (1980-09-01), Pepper

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