Partition of non-volatile memory array to reduce bit line...

Details Partition of non-volatile memory array to reduce bit line... Partition of non-volatile memory array to reduce bit line...

2007-12-25

2007-12-25

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S230030, C365S207000

Reexamination Certificate

active

11078173

ABSTRACT:
The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.

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Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration for International Application No. PCT/US2006/008410, for SanDisk Corporation mailed Jun. 13, 2006.

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