Circuit and method for generating fixed point data with...

Details Circuit and method for generating fixed point data with... Circuit and method for generating fixed point data with...

2007-08-28

2007-08-28

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C714S795000

Reexamination Certificate

active

09986748

ABSTRACT:
A decoding rate is improved while reducing a circuit scale, in a fixed point data generating circuit. When a plurality of floating point data are inputted, for example, the maximum floating point data is detected as a reference data among the plurality of floating point data, in a MAX value detecting circuit10. Then, in an exponent part subtractor20, differences are obtained between the values of exponent parts of the plurality of inputted floating point data and the value of an exponent part of the maximum floating point data. Thereafter, in the shift register30, mantissa parts of the inputted floating point data are shifted by the differences obtained in the exponent part subtractor20, and, in a bit extracting portion40, a predetermined number of bits of the shifted mantissa parts are extracted as fixed point data to be inputted to a Viterbi decoder.

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British Search Report dated May 22, 2002.

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