Low-power high-speed 4-2 compressor with minimized...

Details Low-power high-speed 4-2 compressor with minimized... Low-power high-speed 4-2 compressor with minimized...

2007-10-30

2007-10-30

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10675811

ABSTRACT:
A circuit for use in a microprocessor, comprisinga 4-2 compressor circuit havinga full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells.

REFERENCES:
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patent: 5818747 (1998-10-01), Wong
patent: 6904447 (2005-06-01), Rhee
patent: 7039667 (2006-05-01), Awaka et al.
“A New Low Power CMOS Full Adder”, D. Radhakrishnan, MICC and ISCE '99 Proceedings, Nov. 1999, Melaka, Malaysia, pp. 154-157.

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