High speed serial shift register for MOS integrated circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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365189, 365240, G11C 1928

Patent

active

043226353

ABSTRACT:
A semiconductor device of the MOS/LSI type uses a high speed serial shift register in its input/output system. In a memory device, the serial shift register has a number of stages equal to the number of columns in the memory cell array and is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency.

REFERENCES:
patent: 3497715 (1970-02-01), Yen
patent: 3524077 (1970-08-01), Kaufman
patent: 3638036 (1972-01-01), Zimbelmann
patent: 3898632 (1975-08-01), Spencer, Jr.
patent: 3914750 (1975-10-01), Hadden, Jr.
patent: 3965369 (1976-06-01), Hatsukano
patent: 4044339 (1977-08-01), Berg
patent: 4281401 (1981-07-01), Redwine et al.

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