Multiple high-speed bit stream interface circuit

Details Multiple high-speed bit stream interface circuit Multiple high-speed bit stream interface circuit

2007-08-14

2007-08-14

Vo, Don N. (Department: 2611)

Pulse or digital communications

Transceivers

Transmission interface between two stations or terminals

Reexamination Certificate

active

10625438

ABSTRACT:
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a line side interface, a board side interface, and a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

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patent: WO 02/32005 (2002-04-01), None
Chen, Walter Y. “A Direct Equalization Method”, 1997 IEEE International Conference on Acoustics, Speech and Signal Processing. Speech Processing, Digital Signal Processing. Munich, vol. 3, Apr. 21, 1997-Apr. 24, 1997, pp. 2505-2508, XP000735068; IEEE, New York, NY, USA; ISBN: 0-8186-7920-4.

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