MRAM memory cell having an electroplated bottom layer

Details MRAM memory cell having an electroplated bottom layer MRAM memory cell having an electroplated bottom layer

2007-02-27

2007-02-27

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C365S158000

Reexamination Certificate

active

10761247

ABSTRACT:
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

REFERENCES:
patent: 6172902 (2001-01-01), Wegrowe et al.
patent: 6555858 (2003-04-01), Jones et al.
patent: 6709874 (2004-03-01), Ning
patent: 6716644 (2004-04-01), Nejad et al.
patent: 6743641 (2004-06-01), Yates et al.
patent: 6793961 (2004-09-01), Nikitin et al.
patent: 2003/0119210 (2003-06-01), Yates et al.

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