Semiconductor device having a pixel matrix circuit that...

Details Semiconductor device having a pixel matrix circuit that... Semiconductor device having a pixel matrix circuit that...

2007-10-02

2007-10-02

Lewis, Monica (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S350000, C257S072000, C257S291000, C257S443000, C257SE29202, C257SE29273

Reexamination Certificate

active

09837877

ABSTRACT:
In a CMOS circuit formed on a substrate100, a subordinate gate wiring line (a first wiring line)102aand main gate wiring line (a second wiring line)113aare provided in an n-channel TFT. The LDD regions107aand107boverlap the first wiring line102aand not overlap the second wiring line113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

REFERENCES:
patent: 4609930 (1986-09-01), Yamazaki
patent: 4748485 (1988-05-01), Vasudev
patent: 4977105 (1990-12-01), Okamoto et al.
patent: 4984033 (1991-01-01), Ishizu et al.
patent: 4996575 (1991-02-01), Ipri et al.
patent: 5034788 (1991-07-01), Kerr
patent: 5103277 (1992-04-01), Caviglia et al.
patent: 5124769 (1992-06-01), Tanaka et al.
patent: 5140391 (1992-08-01), Hayashi et al.
patent: 5185535 (1993-02-01), Farb et al.
patent: 5198379 (1993-03-01), Adan
patent: 5233211 (1993-08-01), Hayashi et al.
patent: 5246882 (1993-09-01), Hartmann
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5281840 (1994-01-01), Sarma
patent: 5294821 (1994-03-01), Iwamatsu
patent: 5315132 (1994-05-01), Yamazaki
patent: 5327001 (1994-07-01), Wakai et al.
patent: 5359219 (1994-10-01), Hwang
patent: 5371398 (1994-12-01), Nishihara
patent: 5420048 (1995-05-01), Kondo
patent: 5463483 (1995-10-01), Yamazaki
patent: 5470793 (1995-11-01), Kalnitsky
patent: 5475238 (1995-12-01), Hamada
patent: 5485019 (1996-01-01), Yamazaki et al.
patent: 5506436 (1996-04-01), Hayashi et al.
patent: 5521107 (1996-05-01), Yamazaki et al.
patent: 5532850 (1996-07-01), Someya et al.
patent: 5580802 (1996-12-01), Mayer et al.
patent: 5604368 (1997-02-01), Taur et al.
patent: 5621224 (1997-04-01), Yamazaki et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5646424 (1997-07-01), Zhang et al.
patent: 5702963 (1997-12-01), Vu et al.
patent: 5807772 (1998-09-01), Takemura
patent: 5818076 (1998-10-01), Zhang et al.
patent: 5917221 (1999-06-01), Takemura
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 6054734 (2000-04-01), Aozasa et al.
patent: 6225150 (2001-05-01), Lee et al.
patent: 6252248 (2001-06-01), Sano et al.
patent: 6285042 (2001-09-01), Ohtani et al.
patent: 6323068 (2001-11-01), Seo
patent: 6330044 (2001-12-01), Murade
patent: 6335541 (2002-01-01), Ohtani et al.
patent: 6362507 (2002-03-01), Ogawa et al.
patent: 6365933 (2002-04-01), Yamazaki et al.
patent: 6424012 (2002-07-01), Kawasaki et al.
patent: 6479333 (2002-11-01), Takano et al.
patent: 6534788 (2003-03-01), Yeo et al.
patent: 6590230 (2003-07-01), Yamazaki et al.
patent: 6603453 (2003-08-01), Yamazaki et al.
patent: 6893503 (2005-05-01), Ohnuma et al.
patent: 6998639 (2006-02-01), Ohtani et al.
patent: 7023052 (2006-04-01), Yamazaki et al.
patent: 7138658 (2006-11-01), Yamazaki et al.
patent: 2001/0030722 (2001-10-01), Murade
patent: 2002/0080295 (2002-06-01), Someya et al.
patent: 2002/0093019 (2002-07-01), Hirabayashi et al.
patent: 2003/0038303 (2003-02-01), Hashimoto et al.
patent: 2006/0131583 (2006-06-01), Ohtani et al.
patent: 0 178 447 (1986-04-01), None
patent: 57-032641 (1982-02-01), None
patent: 58-115850 (1983-07-01), None
patent: 60-081869 (1985-05-01), None
patent: 60-154660 (1985-08-01), None
patent: 61-067269 (1986-04-01), None
patent: 61-088565 (1986-05-01), None
patent: 61-220371 (1986-09-01), None
patent: 62-005661 (1987-01-01), None
patent: 62-117359 (1987-05-01), None
patent: 64-019761 (1989-01-01), None
patent: 64-053459 (1989-03-01), None
patent: 64-053460 (1989-03-01), None
patent: 64-059866 (1989-03-01), None
patent: 02-015676 (1990-01-01), None
patent: 03-082171 (1991-04-01), None
patent: 03-256365 (1991-11-01), None
patent: 04-152574 (1992-05-01), None
patent: 04-364074 (1992-12-01), None
patent: 07-130652 (1995-05-01), None
patent: 02-666293 (1997-06-01), None
patent: 2666293 (1997-06-01), None
patent: 10-135468 (1998-05-01), None
patent: 10-135469 (1998-05-01), None
patent: 10-270363 (1998-10-01), None
patent: 10-374878 (1998-12-01), None
patent: 11-354802 (1999-12-01), None
patent: 2000-183356 (2000-06-01), None
patent: 2000-194014 (2000-07-01), None
patent: 2000-196093 (2000-07-01), None
patent: 2000-1940214 (2000-07-01), None
patent: 93/21659 (1993-10-01), None
Peter Van Zant, Microchip Fabrication, 2000, McGraw-Hill, p. 403.
Farrah et al., “Analysis of Double-Gate Thin-Film Transistor”, pp. 69-74, Feb. 1967, IEEE Transactions on Electron Devices, vol. ED-14, No. 2.
Ishii et al., “A Trial Product of Dual-Gate MOS (X MOS) Device”, pp. 405, 1985, 46th Japan Society of Applied Physics, 2a-V-9.
Ishii et al., “Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films”, pp. L521-L523, Apr. 1990, Japanese Journal of Applied Physics, vol. 29, No. 4.
Noguchi et al., “Advanced High Mobility Polysilicon Super-thin Film Transistor (SFT) Using Solid Phase Growth”, pp. 549-552, 1986, Extended Abstracts of the 18th International Conference on Solid State Devices and Materials, Tokyo, B-10-2.
Hayashi et al., “Polysilicon Super-Thin-Film Transistor (SFT)”, pp. L819-L820, Nov. 1984, Japanese Journal of Applied Physics, vol. 23, No. 11.
Hayashi et al., “High Performance Superthin Film Transistor (SFT) with Twin Gates”, pp. 59-62, 1987, Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, A-3-5.
Sekigawa et al., “The Development of XMOS Transistor”, pp. 44-49, 1986, Semiconductor World.
Tuan et al., “Dual-Gate a-Si:H Thin Film Transistors”, pp. 357-359, Dec. 1982, IEEE Electron Device Letters, vol. EDL-3, No. 12.
Specifications and Drawings for U.S. Appl. No. 09/837,552, “Semiconductor Device and Manufacturing Method Thereof”, filed Apr. 19, 2001, Hishashi Ohtani et al.
Specifications and Drawings for U.S. Appl. No. 09/837,558, “Semiconductor Device and Manufacturing Method Thereof”, filed Apr. 19, 2001, Shunpei Yamazaki et al.
Byeon et al.; “High-Performance Tantalum Oxide Capacitors Fabricated by a Novel Reoxidation Scheme”; IEEE Transactions on Electron Devices; vol. 37; No. 4; pp. 972-979.

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