Circuit for selecting/deselecting a bitline of a...

Details Circuit for selecting/deselecting a bitline of a... Circuit for selecting/deselecting a bitline of a...

2007-08-07

2007-08-07

Phan, Trong (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S210130

Reexamination Certificate

active

11120766

ABSTRACT:
A bit-line selection circuit for a memory device includes a decoding line and a dummy line: The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal. The regulating circuit compensates for differences between the programming voltage and the reference voltage.

REFERENCES:
patent: 5917753 (1999-06-01), Dallabora et al.
patent: 6111791 (2000-08-01), Ghilardelli
patent: 6118702 (2000-09-01), Shieh et al.
patent: 6157571 (2000-12-01), Suzuki
patent: 6449191 (2002-09-01), Lin et al.
patent: 7009882 (2006-03-01), Chen

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