Gate line drivers for active matrix displays

Electrical pulse counters – pulse dividers – or shift registers: c – Shift register

Reexamination Certificate

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Details

C377S068000, C377S079000

Reexamination Certificate

active

11302853

ABSTRACT:
A shift register in an amorphous-silicon gate driver comprises a pull-up transistor and two pull-down modules. The pull-up transistor produces a positive pulse when the clock signal is high and the gate of the pull-up transistor is also high. The gate of the pull-up transistor is pulled down to a negative voltage level Vss by two pull-down transistors in the pull-down modules. Each pull-down module also has a further pull-down transistor to keep the output terminal at Vss after the output pulse is produced. The two pull-down modules are operated in a cooperative manner so that each pull-down transistor is conducting approximately 50% of the time. The gates of the pull-down transistors are kept at a positive voltage level approximately 50% of the time and at Vss′ approximately 50% of the time with Vss′ being more negative than Vss.

REFERENCES:
patent: 5517542 (1996-05-01), Huq
patent: 5859630 (1999-01-01), Huq
patent: 5949398 (1999-09-01), Kim
patent: 6747627 (2004-06-01), Koyama et al.
patent: 2004/0046729 (2004-03-01), Moon
patent: 2004/0165692 (2004-08-01), Moon et al.

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