Multilayer printed wiring board

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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Details

C361S794000, C361S803000, C174S267000

Reexamination Certificate

active

11443046

ABSTRACT:
A multilayer printed wiring board10includes: a build-up layer30that is formed on a core substrate20and has a conductor pattern32disposed on an upper surface; a low elastic modulus layer40that is formed on the build-up layer30;lands52that are disposed on an upper surface of the low elastic modulus layer40and connected via solder bumps66to a IC chip70;and conductor posts50that pass through the low elastic modulus layer40and electrically connect lands52with conductor patterns32.The conductor posts50have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts50a, which are positioned at external portions of the low elastic modulus layer40,is greater than or equal to the aspect ratio Rasp of internal conductor posts50b, which are positioned at internal portions of the low elastic modulus layer40.

REFERENCES:
patent: 5509203 (1996-04-01), Yamashita
patent: 5699613 (1997-12-01), Chong et al.
patent: 5916453 (1999-06-01), Beilin et al.
patent: 6384344 (2002-05-01), Asai et al.
patent: 6428942 (2002-08-01), Jiang et al.
patent: 6847527 (2005-01-01), Sylvester et al.
patent: 2006/0180341 (2006-08-01), Kariya et al.
patent: 2006/0231290 (2006-10-01), Kariya et al.
patent: 58-028848 (1983-02-01), None
patent: 05-047842 (1993-02-01), None
patent: 2001-036523 (2001-02-01), None
patent: 2001-298272 (2001-10-01), None
patent: 2003-077920 (2003-03-01), None
patent: 2003-133477 (2003-05-01), None
U.S. Appl .No. 11/415,117, filed May 2, 2006, Kariya et al.

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