Method of fabricating a high-voltage metal-gate CMOS device

Details Method of fabricating a high-voltage metal-gate CMOS device Method of fabricating a high-voltage metal-gate CMOS device

1995-06-14

1996-06-04

Fourson, George

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 57, 437 58, 437 29, 148DIG82, H01L 21265

Patent

active

055232469

ABSTRACT:
A method of fabricating a high-voltage metal-gate CMOS device is disclosed. First, a semiconductor substrate of a first conductivity type having a well region of a second conductivity type is provided. Next, a barrier layer is formed and patterned to form openings for prospective source/drain regions. Then, through the openings, low concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the well region and the semiconductor substrate, respectively. After performing a first thermal treatment, lightly doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively, wherein an oxide layer is also formed within the openings. A sidewall spacer is formed on the sidewalls of the openings. Then, through the openings, high concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the lightly doped source/drain regions of the first conductivity type and the second conductivity type, respectively. After removing the sidewall spacer performing a second thermal treatment, heavily doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively. Further, the barrier layer is patterned to expose areas of the semiconductor substrate and the well region for the prospective gate electrode. Finally, a gate oxide layer and a metal gate electrode are formed.

REFERENCES:
patent: 4851257 (1989-07-01), Young et al.
patent: 5075242 (1991-12-01), Nakahara
patent: 5342794 (1994-08-01), Wei
patent: 5439834 (1995-08-01), Chen

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