Multimode, uniform-latency clock generation circuit

Details Multimode, uniform-latency clock generation circuit Multimode, uniform-latency clock generation circuit

2007-11-27

2007-11-27

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S299000

Reexamination Certificate

active

11394557

ABSTRACT:
A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.

REFERENCES:
patent: 5386392 (1995-01-01), Cantiant et al.
patent: 6850460 (2005-02-01), Chan et al.
patent: 7042672 (2006-05-01), Brenden et al.
patent: 7102408 (2006-09-01), Yamaguchi

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