Sigma-delta modulator for PLL circuits

Details Sigma-delta modulator for PLL circuits Sigma-delta modulator for PLL circuits

2007-10-09

2007-10-09

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S00100A, C341S143000

Reexamination Certificate

active

11363049

ABSTRACT:
A sigma-delta modulator for generating a modulation signal that modulates a frequency division ratio of a comparator/frequency divider of a PLL circuit. Series-connected integrators accumulate an input signal and output overflow signals when their accumulated values exceed a predetermined value. Differentiators transfer the overflow signals of the integrators. An adder multiplies output signals output from the differentiators by a predetermined coefficient and adds the products. A control circuit for transferring the accumulated value in synchronization with a clock signal of each integrator is connected between the integrator of a final stage and the integrator of the preceding stage. The control circuit reduces the modulation width of the modulation signal without reducing the order number of the modulator.

REFERENCES:
patent: 5093632 (1992-03-01), Hietala et al.
patent: 2005/0153662 (2005-07-01), Hasegawa
patent: 2003-023351 (2003-01-01), None
patent: 03/028218 (2003-04-01), None

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