Integrated circuit with resistive network having reduced...

Details Integrated circuit with resistive network having reduced... Integrated circuit with resistive network having reduced...

2007-10-09

2007-10-09

Van Nguyen, Khanh (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including gain control means

C330S086000, C330S307000

Reexamination Certificate

active

11098005

ABSTRACT:
An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by √{square root over (2)}. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

REFERENCES:
patent: 4855685 (1989-08-01), Hochschild
patent: 5905427 (1999-05-01), Hamasaki et al.
patent: 2 039 154 (1980-07-01), None
J. Paul A. Van Der Wagt et al., “A Layout Structure for Matching Many Integrated Resistors”, IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 51, No. 1, Jan. 2004, XP-002306191, pp. 186-190.
Yu Lin et al., “Yield Enhanced Layout Strategies for Ratio-Critical Analog Circuits”, The 2002 45thMidwest Symposium on Cicuits and System, Conference Proceedings, Tulsa OK, XP010635218, pp. I-332 thru I-335.
French Preliminary Search Report dated Nov. 17, 2004 for French Application No. 04 03500.

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