Semiconductor memory having charge trapping memory cells and...

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S185010, C365S190000

Reexamination Certificate

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11145541

ABSTRACT:
In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

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Willer, J., et al., “Novel Virtual Ground Array with Shallow Trench Isolation NROM Architecture.” date unknown, 3 pages.
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Eitan, B., et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.

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