Latency control circuit and method of latency control

Details Latency control circuit and method of latency control Latency control circuit and method of latency control

2007-11-20

2007-11-20

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000

Reexamination Certificate

active

11202314

ABSTRACT:
In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

REFERENCES:
patent: 5614855 (1997-03-01), Lee et al.
patent: 6570814 (2003-05-01), Farmwald et al.
patent: 6615307 (2003-09-01), Roohparvar
patent: 6707759 (2004-03-01), Song
patent: 2002-074961 (2002-03-01), None
patent: 10-0378191 (2003-03-01), None
patent: 10-2004-0005517 (2004-01-01), None

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