Communications: electrical – Digital comparator systems
Patent
1974-04-23
1976-12-07
Shaw, Gareth D.
Communications: electrical
Digital comparator systems
G06F 304
Patent
active
039965619
ABSTRACT:
A priority determination technique for use in a data processing system having a data processor coupled with a plurality of peripheral interface logic elements or boxes for transferring data to such boxes serially by bit, such interface boxes coupled along a daisy chained serial data transfer bus. Each of such boxes is coupled to interface with one or more peripherals for transferring data with the bus. Each interface box includes a priority network including a shift register for receiving bits of the data, wherein a mark bit is initially shifted through the shift register prior to the shifting of the data therein. The interface box address is compared with the respective stages of the shift register and generates a priority signal when the stage containing the mark bit compares with the box address. The priority signal is utilized to provide such highest priority interrupt requesting interface device with sole access for the next data transfer wth the processor.
REFERENCES:
patent: 3752932 (1973-08-01), Frisone
patent: 3818447 (1974-06-01), Craft
patent: 3829839 (1974-08-01), Jeane
patent: 3832692 (1974-08-01), Henzel et al.
patent: 3863220 (1975-01-01), Osawa et al.
Kowal Krzysztof
Malone, Jr. Leon S.
Honeywell Information Systems Inc.
Shaw Gareth D.
Solakian John S.
Vandenburg John P.
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