Semiconductor storage device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S063000

Reexamination Certificate

active

10937440

ABSTRACT:
At least one transistor (MPX) is connected between a plurality of word line driving element circuits formed by using CMOS inverters (MP0and MN0, etc.) and a source potential (Vcc). This transistor (MPX) is independently controlled by a control signal (DECENB) separate from control signals (AB-0to AB-n) of the word line driving element circuits and has both a through current preventing function by adjusting timing and a peak current reducing function by limiting an electric current. Even when all word lines (SWL0to SWLn) are driven at the same time, the electric current is limited and the peak current is suppressed.

REFERENCES:
patent: 5602796 (1997-02-01), Sugio
patent: 6388472 (2002-05-01), Kang
patent: 6477106 (2002-11-01), Fischer et al.
patent: 6608796 (2003-08-01), Weitz
patent: 6914848 (2005-07-01), Jamshidi et al.
patent: 11-177068 (1999-01-01), None
patent: 2000-124782 (2000-04-01), None

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