Systems for increasing register addressing space in...

Electrical computers and digital processing systems: processing – Instruction decoding

Reexamination Certificate

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C712S210000, C712S213000

Reexamination Certificate

active

10978342

ABSTRACT:
A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.

REFERENCES:
patent: 5165038 (1992-11-01), Beard et al.
patent: 5301340 (1994-04-01), Cook
patent: 5613152 (1997-03-01), Van Meerbergen et al.
patent: 6219777 (2001-04-01), Inoue
patent: 6629232 (2003-09-01), Arora et al.
Patterson et al, Computer Organization & Design, 1998, Morgan Kaufman Publishers, 2nd Edition.

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