Method for sampling phase control

Details Method for sampling phase control Method for sampling phase control

Filed on

2007-02-06

Date issued

2007-02-06

Examiner

Vo, Don N. (Department: 2611)

Patent Class

Pulse or digital communications

SubClass

Synchronizers

SubSubClass

Synchronizing the sampling time of digital data

Other Related Categories

C375S376000

Type

Reexamination Certificate

Status

active

Patent number

10219275

Description

ABSTRACT:
Method for sampling phase control for clock and data recovery of a data signal includes sampling a received data signal with a first sampling signal comprising equidistant sampling pulses, minimizing phase deviation between the first sampling signal and the phase of the received data signal to generate an adjusted second sampling signal, and sampling the received data signal with the adjusted second sampling signal to generate sampling data values. The method also includes integrating the sampling data values of the sampled data signal to form a summation value, and altering the phase of sampling pulses of the adjusted second sampling signal until the integrated summation value exceeds a threshold value that can be set.

REFERENCES:
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patent: 6985549 (2006-01-01), Biracree et al.
patent: 2002/0009167 (2002-01-01), Farjad-Rad
patent: 2002/0044618 (2002-04-01), Buchwald et al.
patent: 2003/0123591 (2003-07-01), Walker
patent: 00/11830 (2000-03-01), None
patent: 02/091582 (2002-11-01), None
A 155-MHz Clock Recovery Delay-and Phase-Locked Loop, Thomas Lee and John F. Bulzacchelli, IEEE JSSC, vol. 27, No. 12, Dec. 1992, pp. 1736-1746.
A 30-MHz Hybrid Analog/Digital Clock Recovery in 2-μCMOS, Beomsup Kim, David N. Helman and Paul R. Gray, IEEE JSSC, vol. 25, No. 6, Dec. 1990, pp. 1385-1394.
(3)Clock Recovery from Random Binary Signals, J.D.H. Alexander, Electronics Letters, Oct. 1975, vol. 11, No. 22, pp. 541-542.

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