Semiconductor integrated circuit device

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185120, C365S185170, C365S185250

Reexamination Certificate

active

11443119

ABSTRACT:
A semiconductor integrated circuit device has a memory cell array including a plurality of pages and a page buffer. Each of the plurality of pages includes a user region and a page flag region in which page flag data indicative of a current state of a corresponding page is written. The page buffer includes a user page buffer section which temporarily holds the user data and a page flag page buffer section which temporarily holds the page flag data. The page flag data is recorded in the form of two levels in the non-volatile semiconductor memory cell arranged in the page flag region. The user data is recorded in the form of multilevel in the non-volatile semiconductor memory cell arranged in the user region.

REFERENCES:
patent: 6314026 (2001-11-01), Satoh et al.
patent: 6807104 (2004-10-01), Arai et al.
patent: 6937515 (2005-08-01), Sudo et al.
patent: 7016226 (2006-03-01), Shibata et al.
patent: 7027329 (2006-04-01), Sakuma et al.
patent: 7038946 (2006-05-01), Hosono et al.
patent: 7120052 (2006-10-01), Shibata et al.
patent: 2004-192789 (2004-07-01), None
patent: 2005-243205 (2005-09-01), None
U.S. Appl. No. 11/325,917 filed Jan. 4, 2006, Shibata et al.

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