Stacked semiconductor memory device

Details Stacked semiconductor memory device Stacked semiconductor memory device

2007-04-24

2007-04-24

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S130000, C365S231000, C711S117000, C257S759000

Reexamination Certificate

active

11151213

ABSTRACT:
A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

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Kenji Takahashi, et al.; “Current Status of Research and Development for Three-Dimensional Chip Stack Technology”; Jpn. J. Appl. Phys.; vol. 40; 2001; pp. 3032-3037.

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