Memory device and method for erasing memory

Details Memory device and method for erasing memory Memory device and method for erasing memory

2007-03-06

2007-03-06

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185290

Reexamination Certificate

active

11170950

ABSTRACT:
A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable during an erase process to determine and reduce odd/even wordline offset. The controller operates on separately settable odd/even wordline erase voltages, which are adjusted to affect offset.

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