Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-09-11
2007-09-11
Toledo, Fernando L. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S121000, C438S125000, C438S127000
Reexamination Certificate
active
11265350
ABSTRACT:
A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging. A ground or other reference voltage plane, which is also electrically connected to at least one trace through the anisotropically conductive adhesive layer, may extend over the adhesive layer and frame the cavity, or also extend over the cavity to provide an enclosure for the die. In the former case, an encapsulant is applied over the die and electrical connections to the traces.
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Brooks Jerry M.
Thummel Steven G.
Micro)n Technology, Inc.
Toledo Fernando L.
TraskBritt
LandOfFree
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