Digital storage element architecture comprising integrated...

Details Digital storage element architecture comprising integrated... Digital storage element architecture comprising integrated...

2007-09-25

2007-09-25

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000

Reexamination Certificate

active

11171540

ABSTRACT:
A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.

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Khan, Waheed U. et al., U.S. Appl. No. 10/952,289, filed on Sep. 28, 2004, entitled, “High Speed Energy Conserving Scan Architecture,” 18 pages including 4 pages of Formal Drawings.

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