Electrostatic discharge protection device including...

Details Electrostatic discharge protection device including... Electrostatic discharge protection device including...

2007-05-01

2007-05-01

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000, C361S118000, C257S355000

Reexamination Certificate

active

10944299

ABSTRACT:
ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge reduction circuit (810) in parallel with the discharge circuit. This precharge reduction circuit is operable to cancel any precharge voltage to ground before an ESD event, and also to discharge any trailing pulse to ground after an ESD event. The reduction circuit comprises a discharge resistor (811), preferably about 10 kΩ, connected to the discharge circuit, and a control MOS transistor (812) in series with the discharge resistor. The transistor source (812a) is connected to the resistor, the drain (812b) to ground, and the gate (812c) to core power (813) so that the transistor is shut off during IC operation and conducting when pre-charge or post-charge is present at an ESD pulse.

REFERENCES:
patent: 3806829 (1974-04-01), Duston et al.
patent: 5336908 (1994-08-01), Roberts
patent: 5514919 (1996-05-01), Walley
patent: 5615073 (1997-03-01), Fried et al.
patent: 5946175 (1999-08-01), Yu
patent: 6552886 (2003-04-01), Wu et al.
patent: 6924963 (2005-08-01), Young et al.

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