Data processor

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...

Reexamination Certificate

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Details

C712S213000

Reexamination Certificate

active

10385854

ABSTRACT:
A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

REFERENCES:
patent: 4398245 (1983-08-01), Fujita
patent: 4847759 (1989-07-01), Oklobdzija
patent: 5179691 (1993-01-01), O'Brien et al.
patent: 5313644 (1994-05-01), Matsuo et al.
patent: 5440701 (1995-08-01), Matsuzaki et al.
patent: 5513363 (1996-04-01), Kumar et al.
patent: 5740461 (1998-04-01), Jaggar
patent: 5751991 (1998-05-01), Leach et al.
patent: 5845307 (1998-12-01), Prabhu et al.
patent: 6199155 (2001-03-01), Kishida et al.
patent: 6549999 (2003-04-01), Kishida et al.
patent: 02-293932 (1990-05-01), None
patent: 0 425 410 (1991-05-01), None
patent: 0 426 393 (1991-05-01), None
patent: 0483967 (1992-05-01), None
patent: 58-051353 (1983-03-01), None
patent: 64-048132 (1989-02-01), None
patent: 02-293932 (1990-05-01), None
patent: 3-147021 (1991-06-01), None
patent: 3-150633 (1991-06-01), None
patent: 5-46383 (1993-02-01), None
patent: 05-204635 (1993-08-01), None
patent: 7-175651 (1995-07-01), None
patent: 8-286911 (1996-11-01), None
patent: 09-026878 (1997-01-01), None
patent: 9-512651 (1997-12-01), None
patent: 97/22924 (1997-06-01), None
patent: 97/48041 (1997-12-01), None
“Addressing a Second Page of Registers Without Increasing the Register Field Length,” IBM Technical Disclosure Bulletin, vol. 16, No. 3 (Aug. 1973), pp. 771-772.
“The Hardware Architecture of the Crisp Microprocessor,” by Ditzel et al., The 14th Annual International Symposium on Computer Architecture (Jun. 1987), pp. 309-319.
(ARM THUMB) An Introduction to Thumb™, Mar. 1995, Version 2.0, ARM DVI-0001A, pp. 1-26.

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