Digital signal receiver operating beyond the -3dB frequency

Details Digital signal receiver operating beyond the -3dB frequency Digital signal receiver operating beyond the -3dB frequency

2007-09-25

2007-09-25

Payne, David C. (Department: 2611)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S257000

Reexamination Certificate

active

10483207

ABSTRACT:
A receiver for digital data connects to a preceding signal path and the digital data has a lower to upper data frequency range. The receiver includes a received signal input terminal connected to a higher frequency gain circuit that shows highest transfer amplitude at the upper data frequency within the lower to upper data frequency range where the signal has been attenuated in its higher frequency components in the preceding signal path and providing an amplified signal at an amplified signal output terminal. The receiver further includes a latching circuit with two threshold levels, the latching circuit is connected with an input terminal to the amplified signal output terminal and an output terminal providing a digital output signal.

REFERENCES:
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patent: WO98/20654 (1998-05-01), None
patent: WO98/45955 (1998-10-01), None
K. Koli et al, “An Integrated Cable Equalizer Circuit for 150Mbit/s data transmission”, Helsinki University of Technology, Electronic Circuit Design Laboratory, 1997 IEEE International Symposium on Circuits and Systems.
Routama et al. “A transmitter and receiver interface circuit including an equalizer and PFLL for 150Mbit/s cable communication”. Custom Integrated Circuits Conference May 5, 1997 pp. 315-318.

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