Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-07-31
2007-07-31
Tran, Michael (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
10962588
ABSTRACT:
A method for verifying a programmed flash memory. When reading a memory cell, a voltage applied to a drain of the memory cell is a read drain voltage. First, a word line is enabled by applying a verification gate voltage. Next, a first bit line, which is connected to the drain of the memory cell, is enabled and a verification drain voltage, which is higher than the read drain voltage, is applied to the first bit line. Then, a second bit line is enabled and grounded. Thereafter, a third bit line is enabled and a verification isolation voltage is applied. Then, a drain current of the first bit line is sensed, wherein the drain current flows through the first bit line, the memory cell, and the second bit line. Finally, it is judged whether or not the memory cell is successfully programmed according to the drain current.
REFERENCES:
patent: 2003/0200406 (2003-10-01), Kouno
patent: 2004/0090824 (2004-05-01), Takano et al.
patent: 2004/0184317 (2004-09-01), Miwa et al.
patent: 2004/0246784 (2004-12-01), Yamada
patent: 2004/0257880 (2004-12-01), Yeh et al.
patent: 2005/0057972 (2005-03-01), Taito et al.
patent: 2005/0265081 (2005-12-01), Tran et al.
Chou Ming-Hung
Ho Hsin-Yi
Macronix International Co. Ltd.
Rabin & Berdo P.C.
Tran Michael
LandOfFree
Method for verifying a programmed flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for verifying a programmed flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for verifying a programmed flash memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3763358