Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2007-07-17
2007-07-17
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185190, C365S185220, C365S185240, C365S185250
Reexamination Certificate
active
10988592
ABSTRACT:
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
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U.S. Appl. No. 11/297,467, Dec. 9, 2005, Shibata.
Shibata Noboru
Tanaka Tomoharu
Kabushiki Kaisha Toshiba
Nguyen Viet Q.
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