Chip scale package with micro antenna and method for...

Details Chip scale package with micro antenna and method for... Chip scale package with micro antenna and method for...

2007-05-22

2007-05-22

Estrada, Michelle (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S679000, C257SE33066

Reexamination Certificate

active

11163133

ABSTRACT:
A chip scale package with micro antenna includes a chip, a first dielectric layer and an antenna. The chip has an active surface, a first bonding pad and a second bonding pad on the active surface. The first dielectric layer is formed on the active surface of the chip. The first dielectric layer has a plurality of openings to expose the first bonding pad and the second bonding pad. Each of the openings has an expanding inclined sidewall. The antenna is formed on the upper surface of the first dielectric layer and connected to the first bonding pad and the second bonding pad through the inclined sidewall of the openings for preventing antenna cracking.

REFERENCES:
patent: 6121683 (2000-09-01), Yamazaki et al.
patent: 6580107 (2003-06-01), Asano et al.
patent: 6768190 (2004-07-01), Yang et al.
patent: 6927964 (2005-08-01), Tong et al.
patent: 7056810 (2006-06-01), Yamazaki et al.
patent: 2001/0028103 (2001-10-01), Usami
patent: 2004/0238952 (2004-12-01), Farnworth et al.
patent: 506138 (2002-10-01), None

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