Stacked layered type semiconductor memory device

Details Stacked layered type semiconductor memory device Stacked layered type semiconductor memory device

2007-05-01

2007-05-01

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C365S063000, C365S225700

Reexamination Certificate

active

11038526

ABSTRACT:
To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. As a result, address information can be set afterwards by the program circuit, such that one kind of chips may suffice in the chip manufacturing stage. Because the chip selection signal is inputted in the common chip selection pads, independent wirings for the respective chips are not required.

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